The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7051311 B1

PDF
Full Text
Expired
Date of Patent:
May. 23, 2006

Filed:

May. 28, 2003
Applicants:

Katsuko Tomita, Kawasaki, JP;

Toshiaki Sugioka, Kawasaki, JP;

Katsutoshi Baba, Kawasaki, JP;

Inventors:

Katsuko Tomita, Kawasaki, JP;

Toshiaki Sugioka, Kawasaki, JP;

Katsutoshi Baba, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H01L 29/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention provides a semiconductor circuit designing method, comprising a lower level hierarchical designing step of designing a semiconductor circuit inside a block and an upper level hierarchical designing step of designing an external wiring of the block. The above-mentioned lower level hierarchical designing step or upper level hierarchical designing step includes a shield wiring designing step of designing to provide a shield wiring on a boundary part of the block.


Find Patent Forward Citations

Tomita, Katsuko. (2006). Semiconductor circuit designing method, semiconductor circuit designing apparatus, program, and semiconductor device (U.S. Patent No. 7051311). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7051311

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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