The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 23, 2006
Filed:
Dec. 03, 2003
Gary S. Ditlow, Garrison, NY (US);
Daria R. Dooling, Huntington, VT (US);
Timothy G. Dunham, South Burlington, VT (US);
William C. Leipold, Enosburg Falls, VT (US);
Stephen D. Thomas, Essex Junction, VT (US);
Ralph J. Williams, Essex Junction, VT (US);
Gary S. Ditlow, Garrison, NY (US);
Daria R. Dooling, Huntington, VT (US);
Timothy G. Dunham, South Burlington, VT (US);
William C. Leipold, Enosburg Falls, VT (US);
Stephen D. Thomas, Essex Junction, VT (US);
Ralph J. Williams, Essex Junction, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Disclosed is a method and structure that partitions an integrated circuit design by identifying logical blocks within the integrated circuit design based on size heuristics of logical macros in the design hierarchy. The invention determines whether the number of logical blocks is within a range of desired number of logical blocks and repeats the process of identifying logical blocks for different hierarchical levels of the integrated circuit design until the number of logical blocks is within the range of the desired number of logical blocks. This serves as a guide to partition the chip as opposed to a grid-like partitioning.