The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 23, 2006
Filed:
Jul. 31, 2002
Hung Qui Le, Austin, TX (US);
Alexander Erik Mericas, Austin, TX (US);
Robert Dominick Mirabella, Round Rock, TX (US);
Toshihiko Kurihara, Kanagawa-ken, JP;
Michitaka Okuno, Nagano, JP;
Masahiro Tokoro, Kanagawa, JP;
Hung Qui Le, Austin, TX (US);
Alexander Erik Mericas, Austin, TX (US);
Robert Dominick Mirabella, Round Rock, TX (US);
Toshihiko Kurihara, Kanagawa-ken, JP;
Michitaka Okuno, Nagano, JP;
Masahiro Tokoro, Kanagawa, JP;
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method for determining the latency for a particular level of memory within a hierarchical memory system is disclosed. A performance monitor counter is allocated to count the number of loads (load counter) and for counting the number of cycles (cycle counter). The method begins with a processor determining which load to select for measurement. In response to the determination, the cycle counter value is stored in a rewind register. The processor issues the load and begins counting cycles. In response to the load completing, the level of memory for the load is determined. If the load was executed from the desired memory level, the load counter is incremented. Otherwise, the cycle counter is rewound to its previous value.