Automatic bit-rate detection scheme for use on sonet transceiver

Abstract

An automatic bit-rate detection scheme () for use in SONET/SDH transceivers () that uses only one clocking frequency (clk), is all digital, and requires less than 250 microseconds to detect a new data bit-rate. The present invention analyzes events that are guaranteed to be present in all SONET data streams. A1 and A2 framing bytes () occur at 125 microseconds intervals in all SONET signals. The bit transitions in the framing bytes represent the minimum transition intervals of the received data. The present invention examines this bit interval to determine the operating frequency of the received data. A set of combinational logic circuits () are used to detect specific data bit patterns which appear in the A1 and A2 SONET framing bytes, such as '010' and '101'. The combinational circuit looks for specific patterns of data bits occurring at a specific communication rate. Latches () capture the pulses that are generated by the combinational circuits each time that the particular bit pattern is detected. After sufficient time is passed, the output of the capturing latches indicates which data rates have been detected and logic determines the received data bit-rate, (). A multi-rate chip is then responsively set to communicate at the highest rate detected. The data can be shifted in serially or in parallel.