The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 23, 2006

Filed:

Jul. 15, 2003
Applicants:

Chien-hui Chuang, Taipei Hsien, TW;

Hung-yi Chang, Hsin-Chu, TW;

Yi-hua Chang, Hsin-Chu Hsien, TW;

Inventors:

Chien-Hui Chuang, Taipei Hsien, TW;

Hung-Yi Chang, Hsin-Chu, TW;

Yi-Hua Chang, Hsin-Chu Hsien, TW;

Assignee:

Faraday Technology Corp., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02H 3/00 (2006.01); H02H 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A power supply clamp circuit for preventing damage to an integrated circuit due to electrostatic discharge. The power supply clamp circuit includes a voltage generator electrically connected to a first node for generating a voltage; a first PMOS transistor having a source electrically connected to the first voltage source, a gate electrically connected to the first node, and a drain electrically connected to a second node; a first NMOS transistor having a drain electrically connected to the second node, a gate electrically connected to the first node, and a source connected to ground; a second NMOS transistor having a drain electrically connected to the first voltage source, a gate electrically connected to the second node, and a source connected to ground; and a second PMOS transistor having a source electrically connected to the second node, a gate and a drain commonly electrically connected to the first node.


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