The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 23, 2006
Filed:
Mar. 02, 2004
Siuki Chan, Cupertino, CA (US);
Siuki Chan, Cupertino, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A configurable logic block ('CLB') in a programmable logic device ('PLD'), such as a complex programmable logic device (“CPLD”) or a field programmable gate array (“FPGA”), routes a timing signal, such as an external clock signal, through the CLB to provide a selected delay. The timing signal is routed through selected fast or slow pins of look-up tables (“LUTs”) in the CLB. CLBs are widely available in the PLD, allowing many timing signals to be delayed, and can be configured to account for board-specific or component-specific delays.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile