The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 23, 2006
Filed:
Jun. 01, 2004
Robert J. Chiu, San Jose, CA (US);
Jeffrey P. Patton, Santa Clara, CA (US);
Paul R. Besser, Sunnyvale, CA (US);
Minh Van Ngo, Fremont, CA (US);
Robert J. Chiu, San Jose, CA (US);
Jeffrey P. Patton, Santa Clara, CA (US);
Paul R. Besser, Sunnyvale, CA (US);
Minh Van Ngo, Fremont, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A thin insulating layer is formed over the source/drain junctions. A silicide is formed on the thin insulating layer and on the gate. An interlayer dielectric is deposited above the semiconductor substrate. Contacts are then formed in the interlayer dielectric to the silicide.