The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 23, 2006
Filed:
Mar. 04, 2003
Koichiro Yuki, Osaka, JP;
Tohru Saitoh, Osaka, JP;
Minoru Kubo, Mie, JP;
Kiyoshi Ohnaka, Osaka, JP;
Akira Asai, Osaka, JP;
Koji Katayama, Nara, JP;
Koichiro Yuki, Osaka, JP;
Tohru Saitoh, Osaka, JP;
Minoru Kubo, Mie, JP;
Kiyoshi Ohnaka, Osaka, JP;
Akira Asai, Osaka, JP;
Koji Katayama, Nara, JP;
Matsushita Electric Industrial Co., Ltd., Osaka, JP;
Abstract
An SGelayer (where 0<y<1), an Si layer containing C, a gate insulating film and a gate electrode are formed in this order on a semiconductor substrate. An Si/SiGe heterojunction is formed between the Si and SiGelayers. Since C is contained in the Si layer, movement, diffusion and segregation of Ge atoms in the SGelayer can be suppressed. As a result, the Si/SiGeinterface can have its structural disorder eased and can be kept definite and planar. Thus, the mobility of carriers moving along the interface in the channel can be increased. That is to say, the thermal budget of the semiconductor device during annealing can be improved. Also, by grading the concentration profile of C, the diffusion of C into the gate insulating film can be suppressed and decline in reliability can be prevented.