The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 23, 2006

Filed:

Nov. 03, 2003
Applicants:

Naoki Makita, Nara, JP;

Michinori Iwai, Matsusaka, JP;

Shinya Morino, Ikoma, JP;

Takayuki Tsutsumi, Matsusaka, JP;

Inventors:

Naoki Makita, Nara, JP;

Michinori Iwai, Matsusaka, JP;

Shinya Morino, Ikoma, JP;

Takayuki Tsutsumi, Matsusaka, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/84 (2006.01); H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of the present invention includes the steps of forming an amorphous semiconductor layer on an insulative surface, adding a catalyst element capable of promoting crystallization to the amorphous semiconductor layer and then performing a first heat treatment so as to crystallize the amorphous semiconductor layer, thereby obtaining a crystalline semiconductor layer, performing a first gettering process to remove the catalyst element from the semiconductor layer, and performing a second gettering process that is different from the first gettering process to remove the catalyst element from the semiconductor layer. The first gettering process includes removing at least large masses of a semiconductor compound of the catalyst element present in the crystalline semiconductor layer. The second gettering process includes moving at least a portion of the catalyst element remaining in the crystalline semiconductor layer so as to form a low-catalyst-concentration region in the crystalline semiconductor layer, the low-catalyst-concentration region having a lower catalyst element concentration than in other regions.


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