Method and program for designing semiconductor integrated circuits to optimize clock skews on plurality of clock paths

Abstract

A method for designing semiconductor integrated circuits that efficiently optimizes clock skews in a plurality of clock modes in the case of designing semiconductor integrated circuits having a plurality of clock modes. A plurality of clock paths in each of a plurality of clock modes are detected from layout data for a semiconductor integrated circuit. Delay time in all elements on each of the plurality of clock paths detected is collected. A delay adjustment position is set on each of the plurality of clock paths detected. An optimum delay value at the delay adjustment position on each of the plurality of clock paths is calculated by considering delay time at the set delay adjustment position as a nonnegative variable, by formulating a linear expression for each of the plurality of clock paths by use of this variable and the collected delay time in all of the elements, and by working out the linear expression. Circuit structure based on the layout data is corrected automatically by locating a delay element having appropriate delay time at each delay adjustment position on the basis of the delay value calculated.