Integrated memory having a memory cell array containing a plurality of memory banks, and circuit configuration having an integrated memory

Abstract

An integrated memory has at least two connection panels, which can be operated independently of one another, for external communication by the memory. In addition, a control circuit produces a number of first control signals and a number of second control signals for external tap-off. The number of first control signals corresponds to a number of memory banks. The first control signals are each associated with a memory bank and indicate that an associated memory bank is being accessed. The number of second control signals corresponds to the number of connection panels. One of the second control signals is produced if an access collision occurs between access to one of the memory banks via one connection panel and access to the same memory bank via another connection panel. Two processor units are connected to the connection panels and access the memory independently of one another on the basis of the control signals.