The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 16, 2006
Filed:
Apr. 29, 2004
Kenji Tomiyoshi, Cupertino, CA (US);
Kenji Tomiyoshi, Cupertino, CA (US);
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
A current mode PWM buck regulator is provided. The regulator includes a top-side transistor, a bottom-side transistor, an inductor, a sample-and-hold circuit, a ramp generator, a PWM comparator, an error amplifier, and a current sense amplifier. A current through the low-side transistor is sensed by the current sense amplifier. Also, a current sense voltage provided by the current sense amplifier is sampled when the low-side transistor is on, and held when the low-side transistor is off. The ramp generator is arranged to generate a voltage ramp that emulates the upslope of the inductor current. Additionally, the sampled low-side transistor current is combined with the voltage ramp. The PWM comparator is arranged to provide a PWM signal by comparing the voltage ramp to a comparison signal provided by the error amplifier.