The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 2006

Filed:

Jul. 23, 2004
Applicants:

Bernard L. Grung, Eden Prairie, MN (US);

Wayne L. Walters, Prior Lake, MN (US);

Steven M. Baier, Minnetonka, MN (US);

Inventors:

Bernard L. Grung, Eden Prairie, MN (US);

Wayne L. Walters, Prior Lake, MN (US);

Steven M. Baier, Minnetonka, MN (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G02B 6/36 (2006.01); H04B 17/00 (2006.01); H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A high-speed optical transceiver for an integrated circuit (IC) includes a serializer-deserializer (SERDES) and a vertical cavity surface emitting laser (VCSEL) combined with a detector array. By covalently bonding the SERDES die to the IC, the two components can be processed simultaneously to produce a tightly aligned, high-speed data interface. The SERDES can be coupled to the VCSEL/detector array using a flex interconnect, or the VCSEL/detector array can also be covalently bonded to the IC or SERDES to maximize data bandwidth. The SERDES and VCSEL/detector array can also be produced in a single die using a process technology appropriate for both to maximize manufacturing efficiency.


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