The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 09, 2006

Filed:

Mar. 16, 2001
Applicants:

Eyal Rosin, Rosh Haain, IL;

Regis Hervigo, Vence, FR;

Haim Granot, Bat Hefer, IL;

Inventors:

Eyal Rosin, Rosh Haain, IL;

Regis Hervigo, Vence, FR;

Haim Granot, Bat Hefer, IL;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention is a system in which a multiplicity of diverse dedicated hardware off-core execution units are connected to a core processor in order to increase the speed, power, and flexibility of the processor, and a method of operating the system. Reference instructions executed by the core processor initiate the execution of Configurable Long Instruction Word (CLIW) instructions stored in a CLIW memory. The operation of the off-core execution units is controlled by CLIW instructions. These CLIW instructions may also control operations performed by the core processor, and may be in addition to any other CLIW instructions that control the core processor exclusively. The off-core logic units are operationally connected to the data memory of the core processor under the control of the core processor's data address logic. The use of CLIW technology for the control of the off-core hardware logic units allows the addition of a plurality of diverse off-core logic units without affecting the instruction set, coding space, or instruction decoders of the core processor.


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