The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 09, 2006

Filed:

Sep. 05, 2001
Applicant:

Masayuki Tsuji, Kawasaki, JP;

Inventor:

Masayuki Tsuji, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/00 (2006.01); G06F 7/38 (2006.01);
U.S. Cl.
CPC ...
Abstract

In an SIMD sum of product arithmetic method of enabling a concurrent execution of 2n (where n is a natural number) parallel sum of product arithmetic (operations), the SIMD sum of product arithmetic is executed using 2(m=0, . . . , logn) accumulators as one set, and by replacing a 2p−1th accumulator with an adjacent 2pth (p=1, . . . , n/2) accumulator, without changing a sequence of accumulator addresses, in the set, as accumulator addresses to be allocated to sum of product arithmetic circuits for the SIMD sum of product arithmetic.


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Tsuji, Masayuki. (2006). Simd sum of product arithmetic method and circuit, and semiconductor integrated circuit device equipped with the simd sum of product arithmetic circuit (U.S. Patent No. 7043519). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7043519

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