The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 09, 2006
Filed:
Sep. 06, 2000
William F. Beausoleil, Hopewell Junction, NY (US);
R. Bryan Cook, Poughkeepsie, NY (US);
Tak-kwong NG, Hyde Park, NY (US);
Helmut Roth, Hopewell Junction, NY (US);
Peter Tannenbaum, Woodstock, NY (US);
Lawrence A. Thomas, West Hurley, NY (US);
Norton J. Tomassetti, Kingston, NY (US);
William F. Beausoleil, Hopewell Junction, NY (US);
R. Bryan Cook, Poughkeepsie, NY (US);
Tak-kwong Ng, Hyde Park, NY (US);
Helmut Roth, Hopewell Junction, NY (US);
Peter Tannenbaum, Woodstock, NY (US);
Lawrence A. Thomas, West Hurley, NY (US);
Norton J. Tomassetti, Kingston, NY (US);
Quickturn Design Systems, Inc., San Jose, CA (US);
Abstract
In an emulator processor cluster, the read ports of a shared input and data memory stack are time multiplexed to serve more than one processor. In an exemplary embodiment of the invention, a 256×8 memory array serves as the shared memory for four processors in a cluster. Two read ports are time multiplexed among the four processors in the cluster. On one read cycle, data from the two read ports is coupled to two processors. The next read cycle reads data from the same two ports to the remaining two processors. In the preferred embodiment, the memory operates at twice the system clock speed so that overall emulation process execution time is not effected.