Synchronization control device

Abstract

In a synchronization control device, received ACcoded data or zero data are written into a FIFO buffer in synchronism with bus clock pulses, while yet-to-be-read data are read out from the first-in-first-out buffer. When a difference between the quantity of the yet-to-be-read data in the FIFO buffer and a value represented by synchronization point information is outside an allowable range, a synchronism evaluation section controls a rate of the data readout from the FIFO buffer in such a manner that the difference falls within the allowable range. Synchronization point control section detects leading packet data from among a plurality of successive packet data sequentially arriving in synchronism with the bus clock pulses, and controls the value of the synchronization point information in accordance with a period between the detected leading packet data and next detected leading packet data. With such arrangements, the synchronization control device permits appropriate synchronized reproduction of the received ACcoded data without adverse effects on synchronism evaluation by the synchronism evaluation section.