The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 09, 2006
Filed:
Aug. 06, 2004
James M. Sibigtroth, Round Rock, TX (US);
George L. Espinor, Austin, TX (US);
Bruce L. Morton, Lakeway, TX (US);
James M. Sibigtroth, Round Rock, TX (US);
George L. Espinor, Austin, TX (US);
Bruce L. Morton, Lakeway, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A single memory array () has an isolation circuit for isolating segments of a same bit line (SegBL, SegBL) from each other. The isolation circuit () permits memory cells located in one segment () of an array to be read while memory cells of another segment () of the array are being erased. In one example, the isolation circuit () electrically couples the segments during a read or program of memory cells located on the second segment (SegBL). Program information stored in the single memory array may always be accessed while a portion of the same array is erased. Dynamic variation of the size of the isolated bit line segment occurs when multiple isolation circuits are used to create more than two array segments.