Digital programmable delay scheme to continuously calibrate and track delay over process, voltage and temperature

Abstract

The method and circuit of the present invention compensates a timing change over PVT variations without adverse impact on the system. The method and circuit uses two digital programmable delay circuits which have a Master/Slave relationship. The master programmable delay circuit tracks a delay over PVT and readjusts the delay whenever there is a need for calibration due to PVT variations. The slave programmable delay circuit compensates the timing change by delaying the real clock signal when the master programmable delay circuit completes the delay locking process. The resulting circuit is small, flexible, PVT calibrated, and consumes very little power. It can be used with any reference clock to support various timing requirements at different frequencies.