The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7042087 B1

PDF
Full Text
Expired
Date of Patent:
May. 09, 2006

Filed:

Jul. 18, 2003
Applicants:

Noriaki Sakamoto, Gunma, JP;

Yoshiyuki Kobayashi, Gunma, JP;

Eiju Maehara, Gunma, JP;

Noriyasu Sakai, Gunma, JP;

Hitoshi Takagishi, Gunma, JP;

Kouji Takahashi, Gunma, JP;

Kazuhisa Kusano, Gunma, JP;

Inventors:

Noriaki Sakamoto, Gunma, JP;

Yoshiyuki Kobayashi, Gunma, JP;

Eiju Maehara, Gunma, JP;

Noriyasu Sakai, Gunma, JP;

Hitoshi Takagishi, Gunma, JP;

Kouji Takahashi, Gunma, JP;

Kazuhisa Kusano, Gunma, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 23/495 (2006.01); B23K 31/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

The semiconductor elements for the small signal type circuits and the Au wire for connection are integrated as one package to produce the semiconductor devicesA,A,A,A and. In this way, the wire bonding of Au can be omitted, and the wire bonding of the small diameter Al wire and the large diameter Al wire is only required to complete the connection of the fine metal wire. These semiconductor devices have a plurality of circuit elements as one package, so that the mounting operation on the mounting board can be significantly reduced.


Find Patent Forward Citations

Sakamoto, Noriaki. (2006). Hybrid integrated circuit device (U.S. Patent No. 7042087). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7042087

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