The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 02, 2006
Filed:
Jul. 07, 2000
Applicants:
Hidetoshi Narahara, Osaka, JP;
Seijirou Kojima, Kyoto, JP;
Hiroyuki Tsujikawa, Shiga, JP;
Kenji Shimazaki, Hyogo, JP;
Kasumi Hamaguchi, Osaka, JP;
Inventors:
Hidetoshi Narahara, Osaka, JP;
Seijirou Kojima, Kyoto, JP;
Hiroyuki Tsujikawa, Shiga, JP;
Kenji Shimazaki, Hyogo, JP;
Kasumi Hamaguchi, Osaka, JP;
Assignee:
Matsushita Electric Industrial Co., Ltd., Osaka, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/455 (2006.01);
U.S. Cl.
CPC ...
Abstract
In a gate-level logic simulation, a change in electric current is calculated from event informationoutput from a logic simulatorthrough use of a current waveform calculation section. The thus-calculated change in current is subjected to FFT processing through use of an FFT processing section, thereby determining a frequency characteristic of EMI and enabling EMI analysis.