The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 02, 2006

Filed:

Jun. 10, 2004
Applicants:

Yasuaki Hirano, Tenri, JP;

Shuichiro Kouchi, Tenri, JP;

Inventors:

Yasuaki Hirano, Tenri, JP;

Shuichiro Kouchi, Tenri, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
Abstract

A non-volatile semiconductor memory device includes a memory cell array including a plurality of memory cells, wherein information is writable to each of the plurality of memory cells and information is erasable from each of the plurality of memory cells, and the plurality of memory cells are grouped into at least one memory block; and a write and erasing section for performing a program write operation to a prescribed memory cell in one memory block in a prescribed voltage condition and for performing an erasing operation with respect to the memory cells in the one memory block, wherein the write and erasing section performs a pre-erasing write operation to the memory cells in the one memory block in a voltage condition, which is different from the prescribed voltage condition, before the erasing operation is performed with respect to the memory cells in the one memory block.


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