The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 02, 2006

Filed:

Jun. 21, 2004
Applicants:

Thomas Böttner, München, DE;

Stefan Drexl, Moorenweis-Eismerszell, DE;

Thomas Huttner, Marktoberdorf, DE;

Martin Seck, München, DE;

Inventors:

Thomas Böttner, München, DE;

Stefan Drexl, Moorenweis-Eismerszell, DE;

Thomas Huttner, Marktoberdorf, DE;

Martin Seck, München, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/109 (2006.01);
U.S. Cl.
CPC ...
Abstract

An explanation is given of, inter alia, an integrated circuit arrangement () containing an npn transistor () and a pnp transistor (). Transistors with outstanding electrical properties are produced if the pnp transistor contains a cutout () for an edge terminal region () and if the edge terminal region () has a part near the substrate which is arranged in the cutout () and a part remote from the substrate which is arranged outside the cutout () and overlaps the base terminal region ().


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Böttner, Thomas. (2006). Integrated circuit arrangement having pnp and npn bipolar transistors, and fabrication method (U.S. Patent No. 7038255). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7038255

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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