The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 02, 2006
Filed:
Jun. 16, 2004
Thanas Budri, Portland, ME (US);
Aaron Michael Smith, Harpswell, ME (US);
Neil Suresh Patel, Portland, ME (US);
Loren Charles Krott, Gorham, ME (US);
Thanas Budri, Portland, ME (US);
Aaron Michael Smith, Harpswell, ME (US);
Neil Suresh Patel, Portland, ME (US);
Loren Charles Krott, Gorham, ME (US);
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
A system and method is described for using areas in or near photo global alignment marks or in or near unpatterned areas of a semiconductor wafer to create structures for secondary ion mass spectroscopy (SIMS) testing or electron beam (E-Beam) testing or X-ray diffraction (XRD) testing of the semiconductor wafer. The present invention makes it possible to obtain wafer level information about the front-end processing of the semiconductor wafers. The SIMS/E-Beam/XRD testing measures characteristics such as the dopant content, thickness variations, and defect density of the wafers. The present invention eliminates the need to build individual test structures within product dies and eliminates the need to build scribe line structures near the product dies.