The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 02, 2006
Filed:
Oct. 02, 2003
Frank Dāche, München, DE;
Jochen Dangelmaier, Beratzhausen, DE;
Günter Ehrler, Holzkirchen, DE;
Andreas Meckes, München, DE;
Michael Weber, Mainburg, DE;
Frank Dāche, München, DE;
Jochen Dangelmaier, Beratzhausen, DE;
Günter Ehrler, Holzkirchen, DE;
Andreas Meckes, München, DE;
Michael Weber, Mainburg, DE;
Infineon Technologies AG, Munich, DE;
Abstract
A method for manufacturing a chip housing includes a first basis having a photolithograpically structurable layer on a main face, structured into a cover. A chip has the structure at a main face between first contact elements. A second photolithograpically structurable layer applied to the main face is structured forming a recess surrounded by a wall near the structure exposing the first contact elements. Then, the first basis and the chip are merged with the structure and the cover facing and aligned with each other, and the recess closed by the cover. Removing the first basis leads to an on-chip cavity. Afterwards, a second basis and the chip are merged with the first contact elements connected to the second basis via a conductive structure. Afterwards, the second basis is removed for exposing the conductive structure. The method is less subject to cost and size limitations of known housing technologies.