The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 02, 2006
Filed:
Feb. 16, 2005
Der-tsyr Fan, Hsinchu, TW;
Jung-chang LU, Hsinchu, TW;
Chiou-feng Chen, Hsinchu, TW;
Prateep Tuntasood, Santa Clara, CA (US);
Der-Tsyr Fan, Hsinchu, TW;
Jung-Chang Lu, Hsinchu, TW;
Chiou-Feng Chen, Hsinchu, TW;
Prateep Tuntasood, Santa Clara, CA (US);
Actrans System Inc., Hsinchu, TW;
Actrans System Incorporation, USA, Sunnyvale, CA (US);
Abstract
Flash memory and process of fabrication in which memory cells are formed with select gates in trenches between stacked, self-aligned floating and control gates, with buried source and drain regions which are gated by the select gates. Erase paths are formed between projecting rounded edges of the floating gates and the select gates, and programming paths extend from the mid-channel regions between the select gates and floating gates through the gate oxide to the edges of the floating gates. Trenched select gates can be provided on one or both sides of the floating and control gates, depending upon array architecture, and the stacked gates and dielectric covering them are used as a self-aligned mask in etching the substrate and other materials to form the trenches.