The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 02, 2006

Filed:

Oct. 21, 2004
Applicant:

Tsengyou Syau, Portland, OR (US);

Inventor:

Tsengyou Syau, Portland, OR (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
Abstract

A CMOS structure and a process for forming CMOS devices are disclosed in which gate film stacks are formed over a semiconductor substrate. A barrier layer and a first dielectric film are formed such that they extend over the gate film stacks. Metal lines are formed over the pre-metal dielectric film and spacers are formed that extend on opposite sides of the metal lines. A second dielectric film is formed that extends over the metal lines. A masking structure is formed that defines a contact opening. Selective etch processes are performed to form a self-aligned contact opening, with the adjacent metal lines and spacers aligning the self-aligned contact opening between adjacent gate film stacks. A metal layer is then deposited and planarized to form a self-aligned contact. The masking structure can also define additional contact openings, which are simultaneously etched and filled with metal to form borderless, strapped and shared contacts. These borderless contacts, contacts and shared contacts can either be aligned on one side or can be positioned using only the masking structure.


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