The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 25, 2006
Filed:
Mar. 29, 2002
Thomas M. Mcwilliams, Menlo Park, CA (US);
Jeffrey B. Rubin, Pleasanton, CA (US);
Derek E. Pappas, Union City, CA (US);
Oyekunle A. Olukotun, Stanford, CA (US);
Jeffrey M. Broughton, Palo Alto, CA (US);
David R. Emberson, Santa Cruz, CA (US);
William Kwei-cheung Lam, Newark, CA (US);
Liang T. Chen, Saratoga, CA (US);
Ihao Chen, San Jose, CA (US);
Earl T. Cohen, Fremont, CA (US);
Michael W. Parkin, Palo Alto, CA (US);
Thomas M. McWilliams, Menlo Park, CA (US);
Jeffrey B. Rubin, Pleasanton, CA (US);
Derek E. Pappas, Union City, CA (US);
Oyekunle A. Olukotun, Stanford, CA (US);
Jeffrey M. Broughton, Palo Alto, CA (US);
David R. Emberson, Santa Cruz, CA (US);
William kwei-cheung Lam, Newark, CA (US);
Liang T. Chen, Saratoga, CA (US);
Ihao Chen, San Jose, CA (US);
Earl T. Cohen, Fremont, CA (US);
Michael W. Parkin, Palo Alto, CA (US);
Sun Microsystems, Inc., Santa Clara, CA (US);
Abstract
A computer system for cycle-based computation includes a processor array, a translation component adapted to translate a cycle-based design, a host computer operatively connected to the processor array and to the translation component, a data connection component interconnecting a plurality of members of the processor array using static routing, a synchronization component enabling known timing relationships among the plurality of members of the processor array, a host service request component adapted to send a host service request from a member of the processor array to the host computer, and an access component adapted to access a portion of a state of the processor array and a portion of a state of the data connection.