The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 25, 2006
Filed:
Jun. 03, 2003
Michinobu Nakao, Hitachi, JP;
Ryo Yamagata, Sagamihara, JP;
Kazumi Hatayama, Hitachinaka, JP;
Seiji Kobayashi, Hitachi, JP;
Kazunori Hikone, Naka-machi, JP;
Kotaro Shimamura, Hitachinaka, JP;
Michinobu Nakao, Hitachi, JP;
Ryo Yamagata, Sagamihara, JP;
Kazumi Hatayama, Hitachinaka, JP;
Seiji Kobayashi, Hitachi, JP;
Kazunori Hikone, Naka-machi, JP;
Kotaro Shimamura, Hitachinaka, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
A semiconductor integrated circuit is provided whose area overhead due to provision of test points is reduced together with the test time period. In a semiconductor integrated circuit having a plurality of observation points in a tested circuit, the plurality of observation points are divided into a preset number of groups. The semiconductor integrated circuit contains at least one compressing circuit to reduce the number of bits of a multi-bit signal and to output the result (a signal of less bits) to an observable element such as an external output element or a flip-flop with a scan function. The semiconductor integrated circuit also has at least two scan chains each of which is made up with a plurality of flip-flop circuits working as shift registers. Further, the two scan chains are interconnected with a single input terminal.