The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 25, 2006
Filed:
Dec. 22, 1998
Thomas V Spencer, Ft Collins, CO (US);
Monish S Shah, San Jose, CA (US);
Thomas V Spencer, Ft Collins, CO (US);
Monish S Shah, San Jose, CA (US);
Hewlett-Packard Development Company, L.P., Houston, TX (US);
Abstract
The present invention is generally directed to a device including an asynchronous input/output (I/O) data cache. The device includes a single data storage area that is disposed in communication with both a system data bus and a I/O data bus. Similarly, the device includes an address storage area that is configured to store system addresses corresponding to data contemporaneously stored in the data storage area. The device further includes a first circuit configured to indicate validity status of data within the data storage area for immediate access from the I/O data bus. A similar, second circuit is also included and configured to indicate validity status of data within the data storage area for immediate access from the system data bus. In accordance with another aspect of the present invention, a method is provided for buffering or caching data in a shared relationship between a system data bus and an input/output (I/O) data bus, which includes the steps of providing a single data storage area in communication with both a system data bus and an I/O data bus, and providing a single address storage area configured to store system memory addresses corresponding to data contemporaneously stored in the data storage area. In accordance with the broad aspect of the invention, the method further replicates a portion of validation circuitry in both a system frequency domain and an I/O frequency domain. In this way, latency delays encountered when crossing a frequency domain boundary are encountered at times outside a critical path.