The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7035957 B1

PDF
Full Text
Expired
Date of Patent:
Apr. 25, 2006

Filed:

Dec. 23, 2003
Applicant:

Yasuo Ishiwata, Kahoku, JP;

Inventor:

Yasuo Ishiwata, Kahoku, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/36 (2006.01); G06F 13/38 (2006.01);
U.S. Cl.
CPC ...
Abstract

A PCI bridge circuit connects to first and second PCI buses and performs data transfer between PCI devices. The PCI bridge circuit has a data buffer and controller and the controller, prior to the establishment of a data transfer state with the first PCI device via the first PCI bus, receives data from the second PCI device via the second PCI bus into a data buffer and inserts a wait state. Consequently while reducing the capacity of the data buffer, data transfer between PCI devices can be performed without affecting the transfer performance.


Find Patent Forward Citations

Ishiwata, Yasuo. (2006). Bus bridge circuit, bus connection system, and buffer control method for bus bridge circuit (U.S. Patent No. 7035957). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7035957

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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