The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 2006

Filed:

Oct. 21, 2003
Applicants:

Takanori Mori, Tokyo, JP;

Hirotaka Otsuka, Shounan-machi Higashikatsushika-gun, Chiba 277-0931, JP;

Nobuo Funabiki, Okayama, JP;

Akio Nakata, Osaka, JP;

Teruo Higashino, Osaka, JP;

Inventors:

Takanori Mori, Tokyo, JP;

Hirotaka Otsuka, Shounan-machi Higashikatsushika-gun, Chiba 277-0931, JP;

Nobuo Funabiki, Okayama, JP;

Akio Nakata, Osaka, JP;

Teruo Higashino, Osaka, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01D 3/00 (2006.01); G01M 19/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method and apparatus for generating test sequences for communication protocols that inputs data of finite state machines (FSM) representing the specification of the communication protocols, converts the test sequence generation problem to the satisfiability problem (SAT problem), and generates test sequences for communication protocols by solving the SAT problem. The method converts the test sequence generation problem to the SAT problem by modifying the FSM and describing the test sequence generation problem using a conjunctive normal form formula based on the modified FSIM. By considering multiple input/output (UID) sequences and overlapping sequences, the method generates minimum length test sequence to check whether the states described in the specification of the protocol exist in the implementation of the FSM.


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