Vdd detect circuit without additional power consumption during normal mode

Abstract

In a VDD detect circuit, the output driver interfaces are disabled during power up by pulling the gates of the PMOS interface transistors high using a additional circuitry that operates when VDD is not asserted. The circuit includes a level shifter for controlling the PMOS and NMOS interface transistors during normal mode, and the additional circuitry includes an inverter and a diode string powered by VDDIO, that provides a reference voltage to the level shifter during power up mode. Current flow through the diode string is disabled by a PMOS transistor controlled by VDD, and current flow through the inverter is disabled by the PMOS transistor of the inverter, which is also controlled by VDD. Thus, the additional circuitry provides the enable signal during power up when VDD is not asserted, and does so without causing additional power consumption during normal mode, since the PMOS transistors prevent additional current flow when VDD is high.