The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 25, 2006
Filed:
Feb. 02, 2004
Mario M. Pelella, Mountain View, CA (US);
William George En, Milpitas, CA (US);
Eric Paton, Morgan Hill, CA (US);
Witold P. Maszara, Morgan Hill, CA (US);
Mario M. Pelella, Mountain View, CA (US);
William George En, Milpitas, CA (US);
Eric Paton, Morgan Hill, CA (US);
Witold P. Maszara, Morgan Hill, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. A super-saturated doped source silicide metallic layer is formed on the semiconductor substrate adjacent the gate and the gate dielectric. The silicide metallic layer incorporates a substantially uniformly distributed dopant therein in a substantially uniform super-saturated concentration. The silicide metallic layer is reacted with the semiconductor substrate therebeneath to form a salicide layer and outdiffuse the dopant from the salicide layer into the semiconductor substrate therebeneath. The outdiffused dopant in the semiconductor substrate is then activated to form a shallow source/drain junction beneath the salicide layer. An interlayer dielectric is then deposited above the semiconductor substrate, and contacts are formed in the interlayer dielectric to the salicide layer.