Semiconductor device having optimized shallow junction geometries and method for fabrication thereof

Abstract

The present invention provides, in one embodiment, a method of fabricating a semiconductor device (). The method comprises growing an oxide layer () on a gate structure () and a substrate () and implanting a dopant () into the substrate () and the oxide layer (). Implantation is such that a portion of the dopant () remains in the oxide layer () to form an implanted oxide layer (). The method further includes depositing a protective oxide layer () on the implanted oxide layer () and forming etch-resistant off-set spacers (). The etch-resistant off-set spacers () are formed adjacent sidewalls of the gate structure () and on the protective oxide layer (). The etch resistant off-set spacers having an inner perimeter () adjacent the sidewalls and an opposing outer perimeter (). The method also comprises removing portions of the protective oxide layer () lying outside the outer perimeter () of the etch-resistant off-set spacers (). Other embodiments of the present invention include a transistor device () and method of manufacturing an integrated circuit ().