The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 18, 2006
Filed:
Feb. 19, 2003
Layout correction algorithms for removing stress and other physical effect induced process deviation
Shih-cheng Hsueh, Fremont, CA (US);
Xiao-jie Yuan, Cupertino, CA (US);
Daniel Gitlin, Palo Alto, CA (US);
Shih-Cheng Hsueh, Fremont, CA (US);
Xiao-Jie Yuan, Cupertino, CA (US);
Daniel Gitlin, Palo Alto, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A method for dealing with process specific physical effects applies dimensional modifications to an IC layout to compensate for performance variations caused by the physical effects. Because the dimensional modifications harmonize the performance of the actual IC with the performance of the IC model, time-consuming re-verification operations are not required. Current drive variations caused by shallow trench isolation (STI) stress can be compensated for by adjusting the gate dimensions of the affected transistors to increase or decrease current drive as necessary. Such physical effect compensation can be applied before, after, or even concurrently with optical proximity correction (OPC). The dimensional modifications for physical effect compensation can also be incorporated into an OPC engine.