The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 18, 2006
Filed:
Oct. 17, 2002
Shinya Fujioka, Kawasaki, JP;
Waichiro Fujieda, Kawasaki, JP;
Kota Hara, Kawasaki, JP;
Toru Koga, Kawasaki, JP;
Katsuhiro Mori, Kawasaki, JP;
Shinya Fujioka, Kawasaki, JP;
Waichiro Fujieda, Kawasaki, JP;
Kota Hara, Kawasaki, JP;
Toru Koga, Kawasaki, JP;
Katsuhiro Mori, Kawasaki, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
A memory circuit has: a real cell array; a parity generating circuit for generating a parity bit from data of the real cell array; a parity cell array; a refresh control circuit, which sequentially refreshes the real cell array, and when an internal refresh request and a read request coincide, prioritizes a refresh operation; a data recovery section, which, in accordance with the parity bit read out from the parity cell array, recovers data read out from the real cell array; and an output circuit for outputting data from the real cell array. Further, the memory circuit has a test control circuit, which, at a first test mode, prohibits a refresh operation for the real cell array to output data read out from the real cell array, and, at a second test mode, controls the output circuit so as to output data read out from the parity cell array.