The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 18, 2006

Filed:

Jul. 18, 2002
Applicants:

Tony S. El-kik, Allentown, PA (US);

Richard Joseph Niescier, Bethlehem, PA (US);

Inventors:

Tony S. El-Kik, Allentown, PA (US);

Richard Joseph Niescier, Bethlehem, PA (US);

Assignee:

Agere Systems Inc., Allentown, PA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2006.01); G06F 1/26 (2006.01);
U.S. Cl.
CPC ...
Abstract

The invention is a method and apparatus for minimizing power consumption in a computer peripheral device during suspend state and waking up from suspend state without losing pre-suspend configuration information. The power supply to the peripheral device is split into two power rails, namely, a first rail that is unswitched and a second rail that is switched. The switched power rail provides power to components of the peripheral device other than the bus interface circuit. The unswitched power rail provides power to the bus interface circuit. When the device enters suspend mode, first power is removed from the components other than the bus interface circuit, then all outputs from the other components of the peripheral device to the bus interface circuit and all of the outputs from the bus interface circuit to the other components are forced to logic level 0 so that they do not float during suspend mode, and then finally the clock is disabled. When the device wakes up, power is first restored to the components, then the clock is turned on, and finally the outputs of the various components are released from logic level 0.


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