The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 18, 2006
Filed:
Oct. 13, 2004
Andrew T. Tomerlin, Coral Springs, FL (US);
Nicholas G. Cafaro, Coconut Creek, FL (US);
Robert E. Stengel, Pompano Beach, FL (US);
Andrew T. Tomerlin, Coral Springs, FL (US);
Nicholas G. Cafaro, Coconut Creek, FL (US);
Robert E. Stengel, Pompano Beach, FL (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
A circuit consistent with certain embodiments of the present invention has a source of N reference clock frequencies (), where N is an integer greater than one. N frequency extender circuits () receive the N reference clock frequencies and generating N frequency extended output clock signals therefrom. A plurality of N seed slewers () produce N seed update values. A plurality of N seed registers () each receive one of the N seed update values and produce N seed masks therefrom. A plurality of N logic circuits () each receive one of the N seed masks and one of the N frequency extended output clock signals. Each of the N logic circuits () produce a pseudorandom sequence from the seed mask and the frequency extended output clock signal. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.