The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 18, 2006
Filed:
Dec. 18, 2003
Applicants:
Ankur Bal, Ghaziabad, IN;
Namerita Khanna, Delhi, IN;
Inventors:
Ankur Bal, Ghaziabad, IN;
Namerita Khanna, Delhi, IN;
Assignee:
STMicroelectronics PVT, Ltd., Uttar Pradesh, IN;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/173 (2006.01);
U.S. Cl.
CPC ...
Abstract
This invention relates to a high performance interconnect architecture providing reduced delay minimized electro-migration and reduced area in FPGAs comprising a plurality of tiles consisting of interconnected logic blocks, that are separated by intervening logic blocks. Each set of interconnected logic blocks is linked by an interconnect segment that is routed in a straight line through an interconnect layer over intervening logic blocks and is selectively connected to the logic block at each end through a connecting segment.