The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 18, 2006
Filed:
Oct. 23, 2003
Mark Hollatz, Neustadt, DE;
Klaus-dieter Morhard, Dresden, DE;
Alexander Trüby, Dresden, DE;
Dirk Többen, Munich, DE;
Mark Hollatz, Neustadt, DE;
Klaus-Dieter Morhard, Dresden, DE;
Alexander Trüby, Dresden, DE;
Dirk Többen, Munich, DE;
Infineon Technologies AG, Munich, DE;
Abstract
The invention relates to a method for the planarization of a semiconductor structure comprising a substrate, in which several sub-structures (STI; AA; AA'; AA″;) are provided. said sub-structures (STI; AA; AA′; AA″,) having a first sub-structure (AA′) with planar regions (PS) and first trench regions (DT). A layer to be planarized is applied over the semiconductor structure, said layer having appropriate recesses above the first trench regions (DT) of the first sub-structure (AA′). The method comprises the following steps: pre-planarization of the layer to be planarized by an etching step, using a pre-planarization mask, then subsequent planarization of the layer to be planarized by a chemical-mechanical polishing step. According to the invention, a first region (B) is formed on the layer to be planarized above the first sub-structure (AA′) by means of the pre-planarization mask, said region having a predetermined grid of masked and unmasked sections (M; O) are arranged in such a way that they respectively cover both first trench regions (DT) and planar regions (PS), and a supporting structure for the chemical-mechanical polishing step, which corresponds with the masked sections (M) of the grid, is created by the etching step, using the pre-planarization mask.