The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7027598 B1

PDF
Full Text
Expired
Date of Patent:
Apr. 11, 2006

Filed:

Sep. 19, 2001
Applicants:

Mihailo M. Stojancic, Cary, NC (US);

Mahesh S. Maddury, Santa Clara, CA (US);

Kenneth J. Tomei, Sunnyvale, CA (US);

Inventors:

Mihailo M. Stojancic, Cary, NC (US);

Mahesh S. Maddury, Santa Clara, CA (US);

Kenneth J. Tomei, Sunnyvale, CA (US);

Assignee:

Cisco Technology, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04K 1/00 (2006.01); H04L 9/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A pre-computation and dual-pass modular operation approach to implement encryption protocols efficiently in electronic integrated circuits is disclosed. An encrypted electronic message is received and another electronic message generated based on the encryption protocol. Two passes of Montgomery's method are used for a modular operation that is associated with the encryption protocol along with pre-computation of a constant based on a modulus. The modular operation may be a modular multiplication or a modular exponentiation. Modular arithmetic may be performed using the residue number system (RNS) and two RNS bases with conversions between the two RNS bases. A minimal number of register files are used for the computations along with an array of multiplier circuits and an array of modular reduction circuits. The approach described allows for high throughput for large encryption keys with a relatively small number of logical gates.


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Stojancic, Mihailo. (2006). Residue number system based pre-computation and dual-pass arithmetic modular operation approach to implement encryption protocols efficiently in electronic integrated circuits (U.S. Patent No. 7027598). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7027598

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