Pipeline architecture for multi-slot wireless link processing

Abstract

A wireless communication device processes N Radio Frequency (RF) bursts contained within N slots of a digital communications time divided frame, wherein N is a positive integer greater than one. The wireless communication device includes an RF front end, a baseband processor, and an equalizer module. The RF from end is operable to receive the plurality of received RF bursts and to convert the RF bursts to corresponding baseband signals. The baseband processor operably couples to the RF front end, is operable to receive the baseband signals, is operable to pre-equalization process the baseband signals to produce processed baseband signals, and is operable to post-equalization process soft decisions. The equalizer module operably couples to the baseband processor and is operable to equalize the processed baseband signals to produce the soft decisions. These RF bursts may be contained in adjacent slots or, in non-adjacent slots, or in a combination of adjacent slots and non-adjacent slots.