The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7027066 B1

PDF
Full Text
Expired
Date of Patent:
Apr. 11, 2006

Filed:

Jan. 26, 2005
Applicant:

Mutsuhiro Ohmori, Kanagawa, JP;

Inventor:

Mutsuhiro Ohmori, Kanagawa, JP;

Assignee:

Sony Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06T 15/00 (2006.01); G06T 13/14 (2006.01); G09G 5/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A graphics plotting apparatus which can realize both optimum division of a processing system into blocks and optimum arrangement of the blocks and can be augmented in terms of the performance for a three-dimensional graphics plotting process. The graphics plotting apparatus includes a logic circuit block and a memory block having a capacity sufficient to store display data to be displayed. Both blocks are built in the same chip. An input buffer having a capacity for more than one apex of a three-dimensional graphics plotting primitive is provided, and an interface for transfer of data to and from the outside and the input buffer are arranged on one side of the logic circuit block. A DDA setup circuit is arranged adjacent the input buffer, and a triangle DDA circuit is arranged adjacent the DDA setup circuit. A pair of texture processing circuit blocks are arranged adjacent the triangle DDA circuit. The block sizes of the texture processing circuit blocks are set greater than those of the DDA setup circuit and the triangle DDA circuit.


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