Sample and hold circuit

Abstract

A method and system for sampling an analog signal that minimizes perturbations caused by noise. In one embodiment, the sample and hold circuit includes a plurality of switches in series between the sampled source and a hold capacitor. A resistor is located in parallel with the first switch. The two switches are controlled so as to provide three signal paths between the hold capacitor and the sampled signal. The first signal path is a closed circuit between the charge capacitor and the sampled signal. This path occurs during a first phase of operation for the sample and hold circuit. During a second phase of operation, the first switch is opened which sends any current loss from the capacitor to path through the resistor. The high resistance provided by the resistor minimizes this current loss. The third signal path occurs when the second switch is opened which present an open circuit between the capacitor and the sampled signal. During the transition from the second phase to the third phase, any current loss due to noise passes through the resistor and thus minimizes the voltage loss across the hold capacitor. Another embodiment of the sample and hold circuit only operates between a first and a second phase.