The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 11, 2006

Filed:

Apr. 24, 2003
Applicants:

Mysore Purushotham Divakar, San Jose, CA (US);

David Keating, Limerick, IE;

Antoin Russell, Co. Limerick, IE;

Inventors:

Mysore Purushotham Divakar, San Jose, CA (US);

David Keating, Limerick, IE;

Antoin Russell, Co. Limerick, IE;

Assignee:

Power-One, Inc., Camarillo, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/34 (2006.01); H01L 23/02 (2006.01); H01L 29/76 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor chip package that includes a DC—DC converter implemented with a land grid array for interconnection and surface mounting to a printed circuit board. The package includes a two layer substrate comprising a top surface and a bottom surface. At least one via array extends through the substrate. Each via in a via array includes a first end that is proximate to the top surface of the substrate and a second end that is proximate to the bottom surface of the substrate. At least one die attach pad is mounted on the top surface of the substrate and is electrically and thermally coupled to the via array. The DC—DC converter includes at least one power semiconductor die having a bottom surface that forms an electrode. The power semiconductor die is mounted on a die attach pad such that the bottom surface of the die is in electrical contact with the die attach pad. The bottom of the package forms a land grid array. The land grid array includes external pads that are separated into an interior region and a peripheral region. Each external pad located in the interior region of the land grid array is electrically and thermally coupled a via array.


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