Systems and methods for low leakage strained-channel transistor

Abstract

The present invention facilitates semiconductor fabrication by providing methods of fabrication that mitigate leakage and apply strain to channel regions of transistor devices. A semiconductor device having gate structures, channel regions, and active regions is provided (). Extension regions of a first type of conductivity are formed within the active regions (). Recesses are then formed within a portion of the active regions (). Second type recess structures are formed () within the recesses, wherein the second type recess structures have a second type of conductivity opposite the first type and are comprised of a strain inducing material. Then, first type recess structures are formed () within the recesses and on the second type recess structures, wherein the first type recess structures have the first type of conductivity and are comprised of a strain inducing material.