Method for dicing semiconductor chips and corresponding semiconductor chip system

Abstract

A method for dicing semiconductor chips and a corresponding semiconductor chip system are described. The met-hod includes the steps: provision of a substrate having an upper substrate level, a middle substrate level and a lower substrate level; a plurality of empty spaces or porous areas being provided in the middle substrate level, the empty spaces or porous areas being enclosed by a substrate frame area; the empty spaces or porous areas being situated under a particular semiconductor chip area which is delimited by a semiconductor chip peripheral area in such a way that a particular substrate frame area is distanced from a vertical extension of the particular corresponding semiconductor peripheral area by a lateral intermediate space. In the case of the empty spaces, at least one substrate support element is provided to bond the lower substrate level to a particular semiconductor chip area in the upper substrate level. A lateral separation of the semiconductor chip areas is produced by severing the upper substrate level above the particular intermediate space along the particular semiconductor chip peripheral area. The semiconductor chip areas are diced into semiconductor chips by severing the particular substrate support elements.