The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 11, 2006
Filed:
Dec. 07, 2004
Georg Tempel, Dresden, DE;
Elard Stein Von Kamienski, Dresden, DE;
Stephan Riedel, Dresden, DE;
Veronika Polei, Dresden, DE;
Roland Haberkern, Dresden, DE;
Roman Knoefler, Fishkill, NY (US);
Georg Tempel, Dresden, DE;
Elard Stein von Kamienski, Dresden, DE;
Stephan Riedel, Dresden, DE;
Veronika Polei, Dresden, DE;
Roland Haberkern, Dresden, DE;
Roman Knoefler, Fishkill, NY (US);
Infineon Technologies AG, Munich, DE;
Abstract
The method aims at improving the charge confinement of the memory layer at the edges facing the regions of buried bitlines. After the deposition of the memory layer between confinement layers and the implantation of dopants for bitlines and source/drain regions, an oxidation of semiconductor material to form upper bitline isolation regions takes place. By this method, additional oxide regions are produced at the edges of the memory layer in the same oxidation step. Either a silicon layer may be deposited and reduced to sidewall spacers, which are subsequently oxidized; or recesses are etched into the memory layer and subsequently filled with semiconductor oxide.