The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 11, 2006
Filed:
Feb. 11, 2002
Christophe F. Pomarede, Phoenix, AZ (US);
Michael E. Givens, Phoenix, AZ (US);
Eric J. Shero, Phoenix, AZ (US);
Michael A. Todd, Phoenix, AZ (US);
Christophe F. Pomarede, Phoenix, AZ (US);
Michael E. Givens, Phoenix, AZ (US);
Eric J. Shero, Phoenix, AZ (US);
Michael A. Todd, Phoenix, AZ (US);
ASM America, Inc., Phoenix, AZ (US);
Abstract
Methods are provided herein for forming electrode layers over high dielectric constant ('high k') materials. In the illustrated embodiments, a high k gate dielectric, such as zirconium oxide, is protected from reduction during a subsequent deposition of silicon-containing gate electrode. In particular, a seed deposition phase includes conditions designed for minimizing hydrogen reduction of the gate dielectric, including low hydrogen content, low temperatures and/or low partial pressures of the silicon source gas. Conditions are preferably changed for higher deposition rates and deposition continues in a bulk phase. Desirably, though, hydrogen diffusion is still minimized by controlling the above-noted parameters. In one embodiment, high k dielectric reduction is minimized through omission of a hydrogen carrier gas. In another embodiment, higher order silanes aid in reducing hydrogen content for a given deposition rate.